dwc_pcie5phy_ss5lpe

Description:	PCIe 5.0 PHY, SS SF5 x4, North/South (vertical) poly orientation
Name:	dwc_pcie5phy_ss5lpe_x4ns
Version:	1.04b
ECCN:	5E991/NLR
STARs:	Open and/or Closed STARs
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Product Type:	DesignWare Cores
Overview:	Product Overview Website
Documentation:	Show Documents... Hide Documents... Application Notes SerDes PCB and Packaging Design Guide (Doc Version: 2.70a) ( PDF \| HTML ) Synopsys PHY IP 32G PHY IP Integration Review Checklist Application Notes (Doc Version: 1.50a) ( PDF \| HTML ) Synopsys PHY IP 32G SRAM Adaptation Recording Application Notes (Doc Version: 1.30a) ( PDF \| HTML ) Synopsys PHY IP External ROM and External SRAM Interfaces and Firmware Loading Application Note (Doc Version: 1.30a Raw PCS >= 1.14)) ( PDF \| HTML ) Synopsys PHY IP High-Speed SerDes 32G PHY Gate-Level Simulations (Doc Version: 1.40a ( PDF \| HTML ) Synopsys PHY IP PCIe5 PHY ATE Testbench Application Note (Doc Version: 1.50a (Raw PCS >= 1.16)) ( PDF \| HTML ) Databooks PCIe 5.0 PCS for the DesignWare® Cores PCIe 5.0 PHY x4 for SS5LPE PHY/PCS Wrapper Databook (PCS Version: 1.56a) ( PDF \| HTML ) Synopsys PHY IP PCIe 5 PHY x4 for SS 5LPe Databook (PHY Version: 1.04b_d1) ( PDF \| HTML ) Reference Manual DesignWare® Cores PCIe 5 PHY x4 for SS 5LPe Reference Manual (PHY Version: 1.04b) ( PDF \| HTML ) Release Notes DesignWare® Cores PCIe 5 PHY x4 for SS 5LPe Release Notes (PHY Version: 1.04b) ( TEXT )
Toolsets:	Qualified Toolsets
Download:	dwc_pcie5phy_ss5lpe_x4ns