dwc_comp_ts02p0g02p11saupa256s

Description:	Two Port Ultra Low Power Area Efficient Register File 256K Sync Compiler For TSMC N2P Process
Name:	dwc_comp_ts02p0g02p11saupa256s
Version:	a01
ECCN:	3E991/NLR
STARs:	Open and/or Closed STARs
myDesignWare:	Subscribe for Notifications
Product Type:	DesignWare Embedded Memory IP
Documentation:	Show Documents... Hide Documents... Application Notes Synopsys Memory Compilers Verilog User Guide ( PDF ) TSMC N2P Memory Compilers Read Margin and Assist Settings ( PDF ) Implementation Guide TSMC N2 Memory Compilers tCIC cip variables script ( TEXT ) Release Notes Two Port Ultra Low Power Area Efficient Register File 256K Sync Compiler For TSMC N2P Process - Release Notes ( TEXT ) User Guide Two Port Ultra Low Power Area Efficient Register File 256K Sync Compiler For TSMC N2P Process - User Guide ( PDF )
Download:	v-comp_ts02p0g02p11saupa256s