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ASIP eUpdate February 2026

<p>Synopsys’ solution to efficiently design and implement your own application-specific instruction-set processor (ASIP) when you can’t find suitable processor IP, or when hardware implementations require more flexibility.</p><p>This bi-annual newsletter provides you with easy access to ASIP-related resources.</p>

ASIP Designer

Synopsys’ solution to efficiently design and implement your own application-specific instruction-set processor (ASIP) when you can’t find suitable processor IP, or when hardware implementations require more flexibility.

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This bi-annual newsletter provides you with easy access to ASIP-related resources. This issue includes the following topics:

Technology Feature: Ease-of-Use Improvements For Processor Modeling

In the new release X-2025.12 of ASIP Designer, several enhancements have been added to improve user experience and increase productivity in processor modeling. These enhancements include an nML language server, new convenient features of the ASIP extension for Visual Studio Code, and a more efficient integration of the runtime C library in processor models.

Language server support for nML

The existing language server support in ChessDE, which already provided language-specific smart features for C/C++ code for convenient development of application projects, has been extended to support processor modeling projects as well, by including nML language features.

Once this feature is enabled in the ChessDE preferences menu, in processor modeling projects the ChessDE editor offers language server features for nML, as demonstrated in the screenshot in Figure 1.

Figure 1: nML language server in ChessDE

These features include:

  • symbol information when hovering over a symbol,
  • a symbol outline window,
  • ifdef shading, i.e., shading of code that is currently disabled due to preprocessor settings,
  • live diagnostics of pre-processor errors and nML parsing errors while typing.

Additional features, not shown in the figure, include:

  • navigation to symbol definitions (“Go to definition”),
  • auto-completion of symbol names while typing.

The nML language server features are supported in the ASIP extension for Visual Studio Code as well.

Enhanced ASIP Extension for Visual Studio Code

Next to nML language server support, the ASIP Extension for Visual Studio Code has been enhanced with several features and widgets to improve the user experience when developing ASIP application code in Visual Studio Code.

Release X-2025.12 allows developers to select between different ASIP configurations, which can be defined, stored, and loaded in Visual Studio Code. Figure 2 shows a screenshot of an ASIP configuration view.

Figure 2: ASIP configuration in Visual Studio Code

As shown in Figure 2, an ASIP configuration defines a combination of the processor model project file, the application project file, the compiler configuration, the instruction set simulator, and settings for native debugging. From the ASIP configuration view, icons allow to directly launch compilation or the debugger.

Figure 3: ASIP debugging in Visual Studio Code

Figure 3 shows several new widgets familiar from ChessDE that have been added to the debug view of the ASIP Extension for Visual Studio Code. These widgets include a register view, a statistics view, access to profiling features and runtime checks, and improved error reporting.

Centralized and auto-configurable runtime C library.

The ASIP Designer runtime C library (libm, libc) is now auto-configured from a processor model, via built-in macros, supporting shared library source files.

Previously, the library source files were duplicated per processor model and needed a manual configuration, for example, to adapt limits.h, stdint.h, etc., to the bit widths of the processor’s data types.

Now, the shared library can directly be imported into a processor model, without any file duplication and with automatic configuration, through built-in macros that are generated by ASIP Designer when compiling the processor model. This allows customers to share a centralized runtime C library across multiple processor design projects, and to easily switch to a more recent version of the library, for example, providing support for extra headers.

As the compiler front end can map math functions to any existing processor intrinsics, these intrinsics can be utilized without modifying the central implementation of the runtime library.

The new shared runtime library concept, using auto-configuration, has been applied to all example processor models delivered with ASIP Designer.

What’s New: ASIP Designer X-2025.12 Release

Since the last edition of this newsletter, we have launched a new feature release for ASIP Designer in December 2025, offering various enhancements and extensions. Below is a categorized summary of these updates (ASIP Designer customers can refer to the official Release Notes for a comprehensive list of details). 

Click on each tab for additional information about that new feature

C/C++ Compiler
ChessDE IDE, Instruction-Set Simulation and Debugging
RTL Generation, Verification and Synthesis Support
Example Processor Models
C/C++ Compiler + -

C/C++ Compiler

  • Support for auto-configuration of the runtime C library, allowing for centralized distribution, maintenance, and easy reuse in multiple ASIP design projects. This is complemented with a replacement of some standard function calls by intrinsics. Please see also Section “Technology Feature:  Ease-of-use improvements for processor modeling” above for more details.
  • Support for function promotion to both a list of primitive functions and a single inline stand-alone implementation as fallback.
  • New scheduling options to minimize parallel loads, reducing the number of stall cycles triggered by bank conflicts.
  • The instruction truncation functionality, which deals with variable-length instructions, has been enhanced. The compilers’ code generation phase now better considers the impact of instruction truncation in code-size trade-offs.
  • Support for code-size aware loop unrolling in combination with prepare_for_pipelining, reducing the number of loop versions.
  • The aggressive scheduling mode for processors with an exposed instruction pipeline can now be controlled more precisely to allow servicing of interrupts. By adding “make-interruptible” annotations, aggressive scheduling can be disabled over specific operations or over loop boundaries.
  • Support for linking CHESS object code with third-party linkers on the RISC-V ISA.  This enables the reuse of existing object code libraries for standard RISC-V processors on custom-extended RISC-V processors designed with ASIP Designer.
  • The Chess LLVM front-end and the LLVM library stacks switch to version 21.0.
ChessDE IDE, Instruction-Set Simulation and Debugging + -

ChessDE GUI, Instruction-Set Simulation and Debugging

RTL Generation, Verification and Synthesis Support + -

RTL Generation, Verification, and Synthesis Support

  • Support for hierarchical synthesis with Fusion Compiler.
  • Support for generation of AMD Vivado™ scripts for FPGA mapping.
  • Formal ISA Verification, which was introduced in Release V-2023.12 as part of the Advanced Verification Add-On product, now includes support for stand-alone verification of primitive functions in the datapath validation application (DPV) of VC Formal™, and is now interoperable with Verdi Verification Planner.
Example Processor Models + -

Example Processor Models

The following updates have been made to the library of example processor models:

  • The example models have been auto configured to use a centralized runtime C library.
  • New tutorial demonstrating the use of the GNU linker along with the RISC-V example models.

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