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Synopsys DesignWare USB 2.0 Digital Controller IP Cores

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Synopsys provides designers with silicon-proven, configurable DesignWare® USB 2.0 Controllers that are compliant with the USB-Implementers Forum (USB-IF) USB 2.0 specifications. The DesignWare digital controllers provide: the lowest gate count; power management optimized with dual power rails; and a ULPI interface for discrete PHYs and UTMI/UTMI+ interface for integrated PHYs. This comprehensive solution includes the USB 2.0 LPM-HSIC, OTG, Host and Device Controllers.

The DesignWare USB 2.0 IP is the most certified IP solution in the industry. With over 2,000 design wins and hundreds of millions of silicon-proven units shipped, Synopsys' complete USB IP solution, consisting of digital controllers, PHY and Verification IP, enables designers to lower integration risk and speed time-to-market.

DesignWare Hi-Speed USB On-The-Go Controller Datasheet
DesignWare Hi-Speed USB On-The-Go Controller Subsystem Datasheet
DesignWare Hi-Speed USB On-The-Go Driver Software Datasheet
DesignWare USB 2.0 Device Controller Datasheet
DesignWare USB 2.0 Full Speed On-The-Go Controller Subsystem Datasheet
DesignWare USB 2.0 Host Controller Datasheet
DesignWare USB Link Power Management and High Speed Inter-Chip Datasheet
 

  • Standard Hi-Speed Dual-Role Device operates as either peripheral or host
  • Configuration options to maximize performance and minimize CPU interrupts
  • Flexible parameters enable easy integration into low and high-latency systems
  • Transfer- or transaction-based processing of USB data based on system requirements
  • Configurable data buffering options to fine-tune performance/ area trade-offs
  • Buffer and descriptor pre-fetching maximizes host throughput
  • Firmware-selectable endpoint configurations enable post-silicon application changes and the flexibility of one-chip design for multiple applications
  • Quality IP is tested through extensive Constrained Random Verification
  • AMBA™ High-Performance Bus (AHB) interface enables rapid integration into ARM-based designs
  • UTMI+ Level 3 enables rapid integration with compatible PHYs
  • Hi-Speed (480 Mbps), Full-Speed (12 Mbps), and Low- Speed (1.5 Mbps) operation is compliant to the USB OTG Supplement
  • Supports all OTG features, including Host Negotiation
  • Protocol and Session Request Protocol
  • A separate Hi-Speed USB EHCI Host Controller is also available
USB 2.0 Host Controller Subsystem w/ PCI-AHB Interface Supporting HSICSTARsSubscribe
USB 2.0 Hi-Speed OTG Linux SoftwareSTARsSubscribe
USB 2.0 Hi-Speed OTG Controller Subsystem w/AHB Interface Supporting HSIC (config. as Device only or Full Speed only)STARsSubscribe
USB LPM-HSIC PHY - TSMC 65LPSTARsSubscribe

  Description USB 2.0 Hi-Speed OTG Controller Subsystem w/AHB Interface Supporting HSIC (config. as Device only or Full Speed only)
  Name dwc_usb_2_0_hs_otg_subsystem-ahb
  Version 3.20a
  STARs Open and/or Closed STARs
  myDesignWare Subscribe for Notifications
  Product Type DesignWare Cores
  Documentation
  Toolsets Qualified Toolsets
  Download dw_iip_DWC_otg
  Product Code 3884-0
  
  Description USB 2.0 Hi-Speed OTG Linux Software
  Name dwc_usb_2_0_hs_otg_linux_software
  Version 3.10b
  STARs Open and/or Closed STARs
  myDesignWare Subscribe for Notifications
  Product Type DesignWare Cores
  Documentation
  Download drivers_DWC_otg_linux
  Product Code 4334-0
  
  Description USB 2.0 Host Controller Subsystem w/ PCI-AHB Interface Supporting HSIC
  Name dwc_usb_2_0_host_subsystem-pci-ahb
  Version 2.98a
  STARs Open and/or Closed STARs
  myDesignWare Subscribe for Notifications
  Product Type DesignWare Cores
  Documentation
  Toolsets Qualified Toolsets
  Download dw_iip_DWC_h20ahb
  Product Code 3520-0
  
  Description USB LPM-HSIC PHY - TSMC 65LP
  Name dwc_usb_lpm-hsic_phy-tsmc_65lp
  Version 1.2a
  STARs Open and/or Closed STARs
  myDesignWare Subscribe for Notifications
  Product Type DesignWare Cores
  Documentation
  Download dwc_usb_lpm-hsic_phy-tsmc_65lp
  Product Code 4696-0