USB Link Power Management and High Speed Inter-Chip

The DesignWare® USB Link Power Management (LPM) digital controller and PHY IP implement a new power sleep state which reduces power consumption, by providing faster suspend and resume times by three orders of magnitude (now microseconds instead of milliseconds), compared to the existing USB 2.0 enabled and suspend modes, allowing devices to save power by more frequently turning off the USB connection while idle. The current DesignWare Hi-Speed USB On-the-Go digital controller IP implements multiple power domains, allowing nearly the entire core to be completely turned off while idle. This maximizes battery life by reducing leakage power by 95%.

The DesignWare® USB High Speed Inter-Chip (HSIC) digital controller and PHY IP eliminates the USB cables and connectors, and simplifies the USB connection down to two wires for high speed chip-to-chip communication operating at 480 Mbps. The DesignWare USB HSIC IP remains fully compatible with existing USB software stacks, which allows designers to lower system cost, shorten design time, and improve productivity by reusing existing USB interfaces, drivers and firmware. The DesignWare USB HSIC solution is ideal for applications such as 3G/4G (WiMAX, LTE), smartphones, set-top boxes and mobile internet devices.

Synopsys USB Link Power Management and High Speed Inter-Chip Datasheet



USB Link Power Management IP

  • Reduces power consumption with faster suspend/resume times
  • Lowers overall power and extends battery life of USB-enabled devices
  • Builds on Synopsys expertise in low power methodology and tools

USB High Speed Inter-Chip IP

  • Eliminates cables and connectors
  • Simplifies the USB connection down to two wires
  • Integrated USB HSIC PHY consisting of high speed digital and analog blocks, PLL, and I/O pads, which are delivered as GDSII for advanced processes
  • Offers up to 50% lower power and area by eliminating the need for 3.3V signaling and 5V short precision logic of the USB HSIC PHY