Synopsys has developed a versatile, highly optimized High-Performance Core (HPC) Design Kit comprising a range of specially architected logic cells and memory cache instances that have been optimized specifically to enable stretched SoC's performance and power goals.
While the diversity of compute applications might share the goal of achieving the best PPA, the environmental conditions and design constraints will vary enormously. To meet the latest density and power requirements, high-performance compute, and mobile application processors will harness the latest process nodes, such as 3nm and even 2nm, using complex implementation techniques like dynamic voltage scaling (DVS). This requires wide-range process voltage temperature (PVT) support and may need custom characterization corners for targeted operating points. Automotive and networking compute applications might target slightly larger geometry Fin-FET nodes, like 16nm, 12nm, 7nm, and 5nm, and they can also take advantage of the Synopsys HPC Design Kits to enhance PPA. Crypto engines, graphic processors, and consumer compute engines in 4nm and 6nm shrink processes can also benefit from Synopsys HPC Design Kits.
Figure 1 illustrates Synopsys HPC Design Kit optimized logic library circuits that can significantly benefit the performance and power envelope.