Cloud native EDA tools & pre-optimized hardware platforms
Broadcom’s Tomahawk 51.2 Tbps switch chip, announced in August of 2022, is the latest proof that the 800G Ethernet generation is here. The chip can accommodate the phenomenal bandwidth of 64x 800GbE ports! The evolution of high-speed Ethernet began in 2014 when Arista, Broadcom, Microsoft, Mellanox and Google formed the Ethernet Consortium, now called the “Ethernet Technology Consortium.” Since then, the technology has been adopted by more than 45 members. The push for 200G, then 400G, and now 800G Ethernet is driven by the insatiable need to process and transmit high-performance workloads in diverse applications such as high-performance computing, 5G, and deep learning applications – not to mention the aggregate bandwidth needed to deliver the sum of these applications to and from the cloud. In 2020, the consortium rolled out the 800G specification, which has since been ratified by the IEEE 802.3 standards committee and working group. With the use of high-speed interfaces, hyperscale data centers can support the increasing Ethernet data rates in SoCs for compute rack, switches, retimers, NICs, optical modules, and more. The Ethernet standards provide the reference frame for interoperable interfaces required for design and manufacturing of such SoCs and the devices they support.
There are multitude of ways that an 800G Ethernet controller and PHY solution can meet the scalable and high-data-rate connectivity requirements of data-intensive applications. This article describes a silicon-proven and robust 800G Ethernet implementation using the Synopsys MAC, PCS and PHY IP that companies can use as a reference guide to converge on their own Ethernet SoC design faster.
Figure 1: Switches have evolved from 640G to 102.4T in the last 12 years
Figure 2: 800G pluggables are expected to surpass 400G by 2025
Figure 3: An example of a block diagram for an 800G chip with 8 lanes of 100G Serdes
Figure 4: End-to-end 800G implementation use cases