Why Chip-to-Chip Is Becoming the New Unit of AI Scale

Every hyperscaler and AI silicon team is running into the same problem: workloads are growing faster than any single die, any single server, or any single interconnect can keep up with. Model sizes have outpaced DRAM. Compute has outgrown the reticle. And I/O beachfront is a fixed resource on a chip that is not getting any bigger.

For years, PCI Express has been the heartbeat of high-performance computing — the primary link out of the CPU to accelerators, NICs, memory controllers, and storage. CXL extended that foundation with coherency and memory semantics, becoming the default choice for memory expansion and pooling. Together, these two standards have quietly become the connective tissue of the modern AI data center.

What is changing now is where PCIe and CXL show up. Increasingly, they are the fabric between packaged devices — chip-to-chip (C2C) — not just between the host and its peripherals. That shift is what makes today's designs possible, and it is why architects are re-evaluating how they use these interfaces at every layer of the SoC. 

PCIe for Chip-to-Chip Scale-Out

PCIe remains the most widely available, silicon-proven high-speed serial interconnect on the planet. Off-the-shelf PHYs are available across FPGA and every leading ASIC node, retimers are commodity, and verification methodology is mature. For scale-up between accelerators on a board or within a rack, PCIe delivers the bandwidth, latency, and ecosystem depth that no proprietary link can match — while remaining backwards-compatible generation over generation. Over 2,000 products currently sit on the PCI-SIG Integrators List, and Synopsys PCIe 7.0 IP is already enabling secure data transfers up to 512 GB/s bidirectional in an x16 configuration for the next wave of AI infrastructure.

CXL for Memory Expansion, Pooling, and Coherent C2C

CXL builds on the PCIe SerDes but adds coherency and memory semantics. This is why it has become the interface of choice for memory expansion at the server, memory pooling across the rack, and, increasingly, coherent chip-to-chip extensions between accelerators. Synopsys pioneered the CXS interface with Arm, allowing coherent on-chip protocols to be transported across the CXL link layer with very low latency — a technique now widely used by NoC vendors and customer-proprietary architectures.

Disaggregated Compute

When lane counts and switch requirements exceed what a single package can support, disaggregated compute becomes the topology of choice. PCIe and CXL together form the extended AI fabric — front-end networks, CPU-to-CPU links, switch fabrics, accelerator pools, and memory tiers all connected through the same interoperable ecosystem. This is a shift from a fixed hardware footprint to a flexible, horizontally scalable one.

The pace of the roadmap is one of the most important reasons customers are betting on these standards for their next-generation designs:

• PCIe 6.x (64 GT/s): interop testing began in mid-2026, with mature systems now shipping.
• PCIe 7.0 (128 GT/s): Version 1.0 was ratified in June 2025; pre-FYI interop testing follows in 2027.
• PCIe 8.0 (256 GT/s): The 0.5 draft released June 2026, with v1.0 expected around 2028.
• CXL 3.x (64 GT/s): FYI interop testing begins in 2H 2026.
• CXL 4.0 (128 GT/s): Version 1.0 spec released December 2025, adding memory pooling, port-based routing, and bundled port features.

Every generation is backwards-compatible, and every generation extends the same PHY, controller, and verification IP investment customers have already made. 

Getting past the reticle, memory, and I/O ceilings is only half the story. Once you have decided to build a chip-to-chip fabric with PCIe or CXL, the next question is how — and that is where a lot of the design freedom (and a lot of the tradeoffs) actually live.

There are effectively five ways to run traffic over a PCIe or CXL chip-to-chip link, and each one trades ecosystem leverage against design effort:

• Raw PHYs. Grab a TX/RX pair and stream data. Technically possible — but you own receiver training, link bring-up, speed negotiation, and error handling yourself. Rarely worth it.
• Alternate Protocol Negotiation. Introduced in PCIe 5.0. Trains the link at full PCIe rate, then hands the wire to your protocol. Great for existing protocols being ported onto PCIe SerDes; heavy lift if you are starting from scratch. CXL itself uses this mechanism.
• Traditional PCIe Peer-to-Peer. Fully spec-compliant, but the Root Complex is not required to support peer traffic, so a PCIe switch is effectively mandatory. Works well for small, static topologies where the cost and area of a switch are acceptable.
• Private PCIe Links. A superset of peer-to-peer where the topology is closed and the rules are yours to bend. Overload header fields, upper address bits, tags, routing IDs, and flag bits like Relaxed Ordering or No Snoop. Use Vendor Defined Messages for new packet classes. This is the sweet spot for most AI accelerator arrays.
• Private CXL Links via CXS. Same idea as private PCIe links, but riding the CXL link layer for its low latency. You get access to almost the entire CXL FLIT — 64B in the 68B FLIT mode at 32 GT/s and below, 256B in the 256B FLIT mode at 64 GT/s and above — and the Synopsys CXL controller handles reliable delivery for you.

Because the topology is closed, host software only needs to see the initial endpoint — everything downstream is yours to define. The two main addressing patterns are:

• Host-visible addressing. One shared address space across public and private links. The primary SoC's BAR expands to cover every peer (e.g., 4 SoCs × 4 KB = 16 KB), and the host is guaranteed never to allocate a work item inside that private range. Simple to reason about; can consume a lot of address space at scale.
• Private addressing. Host address space ends at the primary SoC, and the private subsystem uses its own address scheme — one for the whole subsystem, one per link, or something more creative using existing PCIe mechanisms including: TLP Prefix, PASID, overloaded fields, or Vendor Defined Messages.

You don't need a PCIe switch and you don't need to enumerate the private links through a full root complex — the topology is finite and known at build time, so each node can be programmed with its role via strap pins, serial EPROM, or firmware. With the Synopsys PCIe controller, you can even skip PCI configuration cycles entirely on the private side and use back-door access instead. 

The upshot: private topologies give you a full menu of design levers — closed-loop control over routing, addressing, ordering, and flit content — while keeping the ecosystem benefits of PCIe and CXL.

Chip-to-chip fabrics built on PCIe and CXL are not a workaround, they are how AI silicon is being architected now. The reticle wall, the memory wall, and the I/O wall are all being routed around with the same two protocols, and the design freedom is in how you use them: peer-to-peer through a switch, private closed topologies, or coherent extensions carried over the CXL link layer and CXS. Every option leverages the standard intact and the ecosystem, while giving the SoC team room to differentiate where it matters.

The Synopsys PCIe and CXL controllers were designed with these use cases in mind — Native and AXI application interfaces, Vendor Defined Message support, an internal Address Translation Unit, TLP Bypass, and Configuration Intercept — and the same CXS interface carries across to the UCIe solution, so the same architectural decisions travel cleanly from board-level scale-out into the package.

For a deeper walk-through of the topologies and tradeoffs covered here, watch the on-demand webinar: Scaling Compute Connectivity with PCIe and CXL.

More on how it all fits together: Synopsys HPC IP portfolio.