EDA
System
IP
SolvNetPlus
Training & Education
SLM Advanced Clock Generator IP
Clock Generation IP with Advanced DFS/DVFS Capability and Rapid Droop Response
Synopsys SLM Advanced Clock Generator (ACG) IP, part of the Synopsys Silicon Lifecycle Management (SLM) Family, delivers high-performance clock generation designed for droop mitigation and Dynamic Frequency Scaling (DFS)/Dynamic Voltage and Frequency Scaling (DVFS) application. The ACG IP provides ultra-fast adaptive clocking, extensive programmability to address varied use cases, architectures and workloads, and observability to allow monitoring of droop events, DFS/DVFS transitions, and clock health telemetry. Clock telemetry data can be further analyzed and insights applied to enable SLM use cases.
Figure 1: Synopsys SLM Advanced Clock Generator IP
Key Features
- Droop and DFS/DVFS response profile
- Programmable droop and DFS/DVFS response rate
- Interfaces to multi-threshold droop detector
- APB interface for in-field control
- IEEE1149.1/1687 for connection to test fabric
- Core voltage supply
- Comprehensive debug capabilities
- 14-bit fractional output
- Foundry process portable
- 3rd party droop detector support
Key Benefits
- Highly configurable digital architecture reduces clock tree design time
- Fast droop response minimizes droop induced timing failure
- Distributed clocking enables performance tuning per processor type or workload
- Clock-specific telemetry integrates seamlessly with Synopsys SLM ecosystem
This product and/or its use is protected by U.S. Patents: 11496139, 11493950, 11831318, 11070216, 11239849, 11070215, 10594323, 10158365, 10587275, 9698798, 9680480, 9762249, 9705516, 9515668, 9641183 and by copyright law: Portions Copyright © 2025 Movellus, Inc. Used with permission.