Connecting and configuring the IP to create a subsystem is important, but it is equally important to test and verify this new subsystem in the context of the IP and in the context of the SoC. There are several phases of this testing that the IP provider must consider to meet the requirements of the SoC. For example, for many customers the initial phase upon receiving an IP subsystem is to first verify that it functions as specified. Next will be the integration of the IP subsystem into the SoC and verifying interconnectivity, performance tests and for high speed interfaces signal integrity testing (Figure 4). To facilitate these tests, the IP supplier and SoC designer will create an extensive verification plan that clearly outlines and defines all tests with coverage including interconnectivity, interoperability, end-to-end data integrity tests, protocol checks and so on. In this way the SoC designer can easily understand and know which tests they need to port to the SoC level. Additionally, if the IP subsystem includes IP from two different suppliers, the subsystems include additional tests that can identify known interoperability issues and can add assertions for specific events. By performing integrated testing, the IP provider will help designers reduce integration and verification time from several weeks to a few days.
For example, a high-speed interface IP subsystem, such as DDR, typically needs to achieve high levels of performance. At such high data rates a complete system design approach should be undertaken rather than a more limited focus on just the SoC design or package design. Consideration should be given to:
- PCB design, e.g. PCB construction, stack-up, routing, crosstalk, transmission lines and termination
- Packaging, e.g. package type and routing, power integrity, core power and ground
- Power delivery, e.g. power delivery network including considerations for generation of clean supplies including reference and PLL voltages
- Timing budgets
For high-performance DDR interfaces to be successful, extra care must be taken during the design and layout phase to make sure all steps are taken to create a well-controlled signal integrity and power integrity environment. Creating such environments with tight skew control, optimum termination values, and clean reference levels requires a specific skill set and experience that can be provided to ensure signal and power integrity targets can be met for a successful design.