Verify Your SoC Design Efficiently from Planning to Coverage Closure using Synopsys Verification Family

Verifying an SoC is an extremely complex process that requires agile turnaround, constant control feedback, and flexibility to adapt to evolving project needs. Coverage is an efficient metric for the number of potential bugs found and needs to be tracked at each stage of the project. The verification process starts from defining the verification goals, automating test execution, collecting and analyzing coverage metrics, and then tracking and providing guidance until coverage closure is reached. In this webcast, we will describe how to easily achieve this process using the Synopsys Verification Family of tools including VCS, Verdi, and VC Execution Manager.