The coreAssembler product is part of the complete set of IP reuse tools available from Synopsys. coreAssembler provides a graphical or command-based environment that guides the designer through the assembly and configuration of an IP-based subsystem. With coreAssembler, designers can easily generate the configured RTL of a subsystem based on the AMBA IP from the DesignWare Library or from IP with an interface that has been packaged for use with coreAssembler with coreBuilder or has an IP-XACT description of the IP to be integrated. IP that has not been packaged for re-use can also be directly imported into the subsystem. With coreAssembler, you can also easily create and package the complete IP-based subsystem for reuse.


  • Intuitive graphical or command based environment
  • Guides the IP integrator through the assembly of an IP-based subsystem
  • Guides the IP integrator through the configuration of the components contained in the subsystem
  • Generates the RTL configuration and interconnect logic
  • Supports subsystem packaging
  • Includes built-in interfaces to Synopsys tools including:
    • Design Compiler™
    • Physical Compiler™
    • Power Compiler™
    • PrimeTime®
    • Formality®
    • VCS™
    • TetraMAX®
    • Synplify® Premier
  • Flexible TCL interface for tool customization
  • Supports multi-language designs
  • Supports the import of unpackaged IP
  • Automatic generation of the IP-XACT XML representing the subsystem
  • VMM or directed test-bench generation with DesignWare VIP
  • Customizable activity list for design flow customizations