VIP for Compute Express Link (CXL)

Specifications: CXL 4.0/3.0/2.0/1.1

Interfaces: up to PIPE 7, SERDES, up to 32 lanes​

DUT Types/Topology

• Host/ Device - Type 1, Type 2, Type 3
• Support fpr multiple topologies – TL (TLM) only, TL+DL (TLM/LPIF) only, CXL over CXS, Full Stack

Key VIP Features

• API based transaction flow for ease of use
• Native integration with Verdi spec linking (HVP) and Euclide IDE
• PCIe only mode
• Specification linked Functional coverages
• Text file-based configuration setting
• Scoreboard, callbacks and error injection  

Debug and Analysis

• Verdi based protocol and performance analysis
• Protocol checks at each layer
• Debug ports and trace files (transaction/ flits) for each layer (CXL.CM TL/DL, CXL.io TL/DL, Arb mux and PL)
• Separate log for IDE

Available on SoC Verification Kit (SVK) for interoperability and subsystem/SoC level verification using Synopsys IP 

• CXL 4.0
  • Upto 128Gt/s data rate and upto 32 lanes and degraded modes
  • Support of Bundled port and streamlined port
  • Re-timer 3/4 support.
  • Link Layer Initialization, Enumeration or bypass enumeration
  • Support for modelling Configuration Space/Memory mapped Registers
  • All types of IO, Cache and Mem Flows, Back-Invalidation and Host, Device Bias mode
  • Updates to Viral and Poison.
  • IO Throttling updates.
  • IDE, ISL updates
  • Alternate Protocol Negotiation, Framing Error Handling, Synch Header Bypass
  • All Power Saving states
• CXL 3.x
  • Upto 64Gt/s data rate and upto 32 lanes and degraded modes
  • Flit modes: 256B Std/Latency-Optimized flit, 68B
  • CXL Security/IDE support, TSP
  • Switch features (P2P, PBR, GFD, UIO)
  • Link Layer Initialization, Enumeration or bypass enumeration
  • Support for modelling Configuration Space/Memory mapped Registers
  • All types of IO, Cache and Mem Flows, Back-Invalidation and Host, Device Bias mode
  • Retry flow, Viral and Poison, QoS telemetry, Weighted Round Robin
  • Alternate Protocol Negotiation, Framing Error Handling, Synch Header Bypass
  • All Power Saving states

Test Suites / Groups Features

• CXL specification compliance chapter-based test suites for CXL 4.0/3.x/2.0 Host/Device DUT
• Application layer - CXS/native interface for CXL cache/mem and AXI for CXL IO​
• Framework for integration of Synopsys CXL Controller IP as DUT
• PCIe TestSuite Environment as sub env in CXL TestSuite​​