高能效系统级芯片的端到端解决方案

高能效系统级芯片(SoC)已成为所有主要市场的关键需求,从用于移动设备、可穿戴设备、物联网、航空航天和汽车应用的电池供电设备,到用于高性能计算(HPC)、人工智能(AI)、数据中心、网络和存储的有线应用。芯片的能耗影响电池寿命、外形尺寸、散热和冷却成本、功耗与性能的权衡,并最终影响终端产品的碳足迹和燃料消耗,这些因素驱动着许多关键的设计和业务决策。为了实现最佳能效,低功耗技术必须涵盖从芯片到软件的设计和验证的每一个环节。新思科技提供涵盖设计、验证和 IP 产品的端到端高能效 SoC 解决方案

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探索我们的解决方案

<p>Synopsys offers software-driven, low power exploration, analysis and optimization from architecture to signoff. At the early stages of design, Synopsys’ virtual-prototyping solutions enable system architects to explore and tune the macro-architecture and embedded software for low power. Software workloads can then be profiled in the power emulator to identify key windows of interest for downstream power analysis and optimization. A comprehensive solution for RTL power exploration and analysis can be used to further tune the micro-architecture for low power. Automatic power-optimization techniques in the RTL-to-GDSII implementation flow ensure that design meets power-performance-area (PPA) targets followed by high-accuracy power signoff. The entire flow supports UPF (IEEE 1801) low power intent.</p>

设计高能效 SoC

新思科技提供从架构到签核的软件驱动低功耗探索、分析和优化方案。在设计的早期阶段,新思科技的虚拟原型解决方案使系统架构师能够探索并调整宏观架构和嵌入式软件以实现低功耗。随后,可以在功耗仿真器中对软件工作负载进行分析,以识别下游功耗分析和优化的关键窗口。针对 RTL 功耗探索和分析的综合解决方案可进一步调整微架构以降低功耗。在 RTL 到 GDSII 的实现流程中,自动功耗优化技术确保设计满足功耗-性能-面积(PPA)目标,并进行高精度功耗签核。整个流程支持 UPF(IEEE 1801)低功耗意图。

<p>Synopsys offers a comprehensive low power verification solution based on UPF (IEEE 1801) power intent. This includes verification of the UPF low power intent and exhaustive functional verification of the design in the presence of low power techniques expressed in UPF. The solution spans static verification for low power checks, UPF-aware formal verification, low power simulation, early SoC architecture analysis, and optimization for power, emulation and prototyping. Integrated with the verification solution is a unified low power debug, planning and coverage solution to ensure that designers can effectively root-cause low power bugs and also ensure the design meets its functional coverage goals.</p>

验证高能效 SoC

新思科技提供基于 UPF(IEEE 1801)低功耗意图的全面低功耗验证解决方案。这包括对 UPF 低功耗意图的验证,以及在应用 UPF 所表达的低功耗技术时对设计进行全面的功能验证。该解决方案涵盖低功耗检查的静态验证、支持 UPF 的形式验证、低功耗仿真、早期 SoC 架构分析,以及针对功耗的优化、仿真和原型验证。该验证解决方案集成了统一的低功耗调试、规划和覆盖功能,确保开发者能够有效定位低功耗问题,并确保设计满足功能覆盖目标。

IP + -
<p>With semiconductor IP, designers can incorporate the most advanced functionalities in their complex SoCs for a wide range of applications including mobile, automotive, and high-performance computing (HPC). SoCs for battery-operated devices and high-end compute systems require IP that offers maximum energy efficiency while maintaining high performance. Synopsys’ DesignWare® Interface, Foundation and Processor IP portfolio supports a wide-range of power features and is designed with the latest advanced low power techniques, including multi-voltage design, power-gating, configurability, and more.</p>

IP

新思科技针对低功耗 SoC 提供的 IP,使设计人员能够通过提供广泛的接口、基础和处理器 IP,构建高性能、高能效的芯片。这些解决方案支持先进的节能技术和可配置功能,帮助优化性能,同时将嵌入式系统和 SoC 应用的功耗降至最低。

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