Accelerating Static ESD Simulation for Full-Chip and Multi-Die Designs with Synopsys PathFinder-SC

PST: 8:00 – 9:00 AM | CET: 5:00 PM

Featured Speakers:

• Peter Tsai, Product Manager, Synopsys
• Marc Swinnen, Product Marketing Manager, Synopsys
• John Alwyn, Product Specialist, Synopsys

As semiconductor complexity accelerates with advanced nodes, chiplets, and 3DIC integration, robust ESD protection requires verification earlier in the flow. Synopsys PathFinder-SC shifts signoff simulations to earlier design stage using cell-based modeling of discharge circuits derived from GDS/OASIS of design and/or place & route design data (DEF/LEF). This combines certified accuracy with cloud-native capacity to handle effective resistance, current density, and CDM checks across full-chip and multi-die designs.

PathFinder-SC uses the same extraction and EM calculation engine with Synopsys RedHawk-SC certified by major foundries which can help detect potential silicon failures. Its layout-based debugging and compact modeling extend reliability from die to package to board. Seamlessly integrated into modern verification flows, PathFinder-SC empowers teams to accelerate signoff, mitigate risk, and deliver future-proof designs for HPC, AI/ML, and 5G/6G systems.

Join our PathFinder-SC webinar to see how you can:

• Perform pre-LVS, cell-based ESD checks early in the flow
• Handle full-chip and multi-die designs with cloud-native capacity
• Use a foundry certified solution and layout-based debugging for reliability from die to board
• Accelerate signoff, reduce risk, and future-proof your designs