How PCIe Multistream Architecture is enabling AI Connectivity at 64 GT/s and 128 GT/s

Featured Speaker:

• Diwakar Kumaraswamy, Sr. Staff Technical Product Manager, Synopsys

AI and HPC workloads push fabric speeds to deliver higher parallelism and utilization at extreme data rates. To support these higher rates, the controller architecture needs to be completely redefined resulting in the new PCIe controller Multistream architecture where multiple TLP streams to be serialized over the link. This shift from the single-stream model of prior generations impacts how application interfaces and user logic are designed.

In this webinar, we will examine the architectural differences compared to controller’s architecture limited to 32GT/s or less, focusing on how multiple application interfaces are supported, their effect on link utilization, and the mechanisms for maintaining ordering across streams.

We will also analyze the implications for FLIT versus Non-FLIT mode, along with practical considerations for AXI bridge configuration under the new architecture. 

Why You Should Attend:

• Understand Industry Bottlenecks
• Explore Practical Integration Solutions
• Gain Design-Level Insights

Register now to deepen your understanding of PCIe Multistream operation and make informed design choices for AI and HPC SoCs at the interface and system levels.