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Training & Education
Meta: Multi-Die Partitioning and Floorplanning Prior to Netlist Using 3DIC Compiler
Featured Speakers:
- Sivanandh Ramadass, Principal Engineer , Meta
- Gireesh Vijayakumar, Silicon Technical Lead , Meta
In this Synopsys Webinar, Meta will present how an architecture‑driven methodology, originally presented at Synopsys Converge, enables early exploration and definition of complex 2.5D and 3D multi‑die designs before netlists or process details are available. Meta will share how architects use a lightweight, spreadsheet‑based interface combined with Synopsys 3DIC Compiler to rapidly evaluate die partitioning, floorplans, and die‑to‑die connectivity with early physical awareness. The session highlights how shifting critical decisions upstream helps reduce risk, avoid late‑stage rework, and accelerate convergence on manufacturable, high‑performance multi‑die designs.
What you'll learn:
- How Meta explores multi-die designs without a netlist
- Why early partitioning and floorplanning are critical in 2.5D/3D designs
- How physical awareness reduces late-stage congestion, SIPI, and thermal risk
- How AI-driven analysis supports faster, data-driven architectural decisions
Register Now!
Featured Speakers
Sivanandh Ramadass
Principal Engineer, Meta
Sivanandh Ramadass is a Silicon Technical Lead at Meta, specializing in SoC flow methodology and RTL-to-GDS implementation for advanced AI accelerator chips powering Meta data centers. He has 25 years of experience in physical design implementation and methodology at both full-chip SoC and partition levels, and has led multi-disciplinary teams delivering end-to-end physical design execution—including floorplanning, partitioning, and signoff closure—on leading-edge process nodes. Sivanandh’s strengths include methodology ownership (RTL-to-GDS flows, signoff policies, and closure strategies) and cross-organization technical leadership, aligning architecture, RTL, and backend teams to deliver scalable, hyperscale deployments. Prior to Meta, he held technical roles at Qualcomm and AMD, contributing to Snapdragon and Radeon GPU SoCs.
Gireesh Vijayakumar
Silicon Technical Lead, Meta
Gireesh Vijayakumar is a Silicon Technical Lead at Meta, specializing in SoC flow methodology and RTL-to-GDS implementation for advanced AI accelerator chips powering Meta data centers. With 18+ years of experience across Meta, Apple, and Qualcomm, he has led multi-disciplinary teams delivering full-chip physical design execution—including floorplanning, partitioning, and signoff closure—on the latest process nodes. His strengths include methodology ownership (RTL-to-GDS flows and signoff policies), power/reliability signoff (PI, PDN strategy, IR/EM, and 3DIC reliability), and cross-org leadership aligning architecture, RTL, and backend teams for hyperscale deployments.