Intel: From Construction to Signoff: 3DIC Methodology for Disaggregated Designs

Featured Speaker:

• Victoria Kolesov, Design Automation Principal Engineer, Intel

In this Synopsys webinar, Intel will present how its disaggregated designs across client and server platforms have driven the evolution of robust 3D multi-die design construction and signoff methodologies. Intel will share practical experience using Synopsys’ complete design implementation and signoff flows for static timing analysis signoff and 3D layout verification in both passive and active interposer designs. The session highlights how increasing accuracy requirements have shaped 3D construction practices, standards, and collateral, enabling consistent, correct‑by‑construction signoff across process nodes, TSVs, and complex die‑to‑die interconnects.

What you’ll learn:

• How Intel approaches 3DIC construction for disaggregated designs
• Key requirements for static timing and layout signoff in 3DIC flows
• Differences between passive and active interposer signoff considerations
• How accuracy requirements influence 3D construction methodologies
• Best practices for achieving correct‑by‑construction 3DIC signoff