Enabling Informed Processor Core Selection through Early Architecture Analysis

Custom silicon designers face the daunting task of selecting and configuring third-party IPs from a vast array of options, while ensuring compatibility and integration with their System-on-Chip (SoC) design. To address this challenge, Meta employed a comprehensive approach using SNPS Platform Architect, examining three key axes: core type, core configuration, and SoC memory hierarchy optimizations.

By defining and analyzing Key Performance Indicators (KPIs) such as IPC/runtime, CSR writing throughput, and memory-bound BW, Meta identified the optimal configuration that balances performance and power consumption. Furthermore, our study revealed opportunities for simplifying IP configuration through memory hierarchy optimizations, resulting in reduced memory latency and smaller IP cache/area.

This holistic approach enables early architecture design exploration and optimization, facilitating the identification of potential issues and opportunities for improvement. By adopting this methodology, custom silicon designers can reduce development costs and accelerate time-to-market, ultimately driving innovation in the field.