Scaling Compute Connectivity with PCIe and CXL: Chip-to-Chip and Emerging Architectures

Featured Speakers:

• Richard Solomon, Senior Staff Technical Product Manager, Synopsys
• Ron Lowman, Staff Product Manager, Synopsys

Heterogeneous compute platforms are driving new requirements for connectivity across increasingly complex system architectures. This webinar explores how PCIe and CXL can be used to provide efficient and high-performance chip-to-chip connectivity, across host-to-memory, host-to-networking, host-to-host, and host-to-accelerator designs in conjunction with popular die-to-die technologies. We will examine key physical, application, and protocol interface considerations, and how interface IP choices impact latency, power, cost, and scalability. The session will also highlight emerging use cases across accelerators, SSDs, CPU-to-CPU communication, and multi-die or disaggregated platforms including the rapidly evolving ecosystems.  Attendees will gain practical insight into selecting and deploying the right interface IP to optimize system performance and prepare for next-generation scalable compute architectures.

What You'll Learn:

• Key chip-to-chip architectures and how interface IP enables scalable system design
• Differences between physical, application, and protocol interfaces—and their impact on integration
• How emerging use cases like accelerators, SSDs, and multi-die systems are shaping IP and connectivity decisions
• Tradeoffs between PCIe, CXL, and other interface IP for performance, power, and latency