Achieve First-pass Silicon Leveraging SDC Verification Early with No Noise

As today’s designs are getting more complex, design constraints complexity also increases multifold. While ensuring design correctness typically gets a lot of attention including code review, functional verification, implementation, etc., correctness of constraints requires the same level of attention. Quality of implementation and timing analysis is highly dependent on quality of constraints. For achieving first-past silicon efficiently, it is imperative to ensure that the constraints are correct and complete early at RTL before progressing to late design stages of implementation and timing analysis. 

In this presentation, we will focus on the conceptual foundations of constraints verification at RTL using Synopsys Timing Constraints Manager. Further, we will cover the types of constraints issues flagged and noise reduction techniques using built in formal verification. Lastly, we will discuss the need for timing exception verification (MCP/FP) and the use of formal and simulation techniques to deliver complete verification results to pinpoint incorrect timing exceptions.