Synopsys Ultra High-Performance AES-XTS/ECB IP Core Datasheet

The Synopsys AES-XTS/ECB IP datasheet details two high-performance cores—supporting up to 4096 bits/cycle, 64K interleaved streams, and seamless integration with DDR/LPDDR/HBM controllers for inline memory security. Download the datasheet.

What You Will Learn:

Architecture: pipelined, unidirectional/bidirectional, with message interleaving and secure key loading
Modes: AES-XTS, AES-ECB, and optional SM4-XTS; 128/256-bit keys; CTS and ECC latency parametrization
Memory and performance: two-port/single-port support, optimized gate count, and 1 tweak/cycle precomputation
Security: FIPS 140-3 certification ready, NIST CAVP validated

Download Now

ASK

BETA

End Chat

Closing this window clears your chat history and ends your session. Are you sure you want to end this chat?

Legal Disclaimer

NOTICE: You are interacting with an AI-powered chatbot that provides general information about Synopsys, including its products and services, which may be incorrect or incomplete. In the event of any conflict or discrepancy, the terms of your applicable agreements supersede any information provided by this chatbot. These chats may be accessed by Synopsys and its service providers to customize the experience and improve this tool, and your use of this chatbot is an agreement to that data processing activity.