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Synopsys Ultra High-Performance AES-XTS/ECB IP Core Datasheet

The Synopsys AES-XTS/ECB IP datasheet details two high-performance cores—supporting up to 4096 bits/cycle, 64K interleaved streams, and seamless integration with DDR/LPDDR/HBM controllers for inline memory security. Download the datasheet.

What You Will Learn:

Architecture: pipelined, unidirectional/bidirectional, with message interleaving and secure key loading
Modes: AES-XTS, AES-ECB, and optional SM4-XTS; 128/256-bit keys; CTS and ECC latency parametrization
Memory and performance: two-port/single-port support, optimized gate count, and 1 tweak/cycle precomputation
Security: FIPS 140-3 certification ready, NIST CAVP validated

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