EDA
System
IP
SolvNetPlus
Training & Education
Synopsys PHY IP for PCI Express 3.1 Datasheet
Download the Synopsys PCIe 3.1 PHY IP datasheet and learn how a silicon-proven, multi-lane PHY delivers robust signal integrity, low power, and on-chip diagnostics—optimized for x1–x16, SRIS, and advanced equalization.
What You Will Learn:
- How to configure x1–x16 PHYs with PIPE macro aggregation, bifurcation, and single/multi-clock domains
- The impact of multi-tap, adaptive CTLE/DFE on link margin, crosstalk immunity, and PVT robustness
- Power management: L1 substate, power island, and DFE bypass for area- and energy-sensitive designs
- Integration flow: programmable Tx/Rx equalization, flexible reference clocks, and support for wirebond or flip-chip---
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