Addressing Physical Verification for Multi-Die Designs

Multi-die designs using 2.5D and 3D technologies are increasingly important for a wide range of electronics applications, including high-performance computing (HPC), artificial intelligence (AI), automotive, and mobile. Multi-die design enables designers to mix dies (also called chiplets) from different foundries and technology nodes, including existing dies from previous projects in a single package.

The resulting density, compute power, and interconnect speeds are much greater than those achievable with traditional monolithic dies. However, multi-die design presents novel issues and challenges that need to be addressed.

This white paper focuses on the physical verification of multi-die designs from one die to multiple dies in a package.