Synopsys Multi-Protocol 10G PHY IP Datasheet

Download the Synopsys Multi-Protocol 10G PHY IP datasheet and see how a silicon-proven, small-area PHY delivers robust signal integrity, continuous calibration, and advanced testability in 16nm/14nm and below.

What You Will Learn:

• How to implement x1–x16 lane configurations with PCIe aggregation, bifurcation, and lane margining
• The effect of adaptive CTLE/DFE/FFE, hybrid transmit drivers, and CCA for robust link performance across voltage/temperature
• Power management: L1 sub-states, power gating, voltage mode underdrive, and low standby current
• Integration flow: single clock domain for multi-lane PHY, PCS blocks for PCIe/SATA/Ethernet, and TAP/JTAG debug---