EDA
System
IP
SolvNetPlus
Training & Education
Synopsys Multi-Port Switch IP for PCI Express Datasheet
Download the Synopsys Multi-Port Switch IP datasheet and see how a fully synthesizable, parameter-rich solution delivers non-blocking peer-to-peer traffic, cut-through buffer mode, and up to 32 GT/s across x1–x16 ports—optimized for enterprise, storage, and embedded platforms.
What You Will Learn:
- How to configure multiple downstream ports, lane widths, and bus widths for optimal system architecture
- Techniques for supporting SR-IOV/ARI (up to 64K virtual functions), 8 traffic classes, and up to 8 virtual channels
- Power and latency optimization: ASPM, L1 sub-states, OBFF/LTR ECN, power gating, and cut-through buffer mode
- Integration flow: Verilog RTL, UVM environment, design team guidance, and comprehensive documentation
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