Synopsys DDR4 multiPHY IP Datasheet

Download the Synopsys DDR4 multiPHY IP datasheet and see how a silicon-proven, GDSII-delivered hard PHY—plus RTL-based PUB—enables up to 2667 Mbps, per-bit deskew, and seamless support for DDR4, DDR3(L/U), LPDDR2/3, and multi-channel/PoP systems.

What You Will Learn:

• How to implement a JEDEC-standard, DFI 3.1-compliant PHY supporting DDR4 (2667 Mbps), DDR3/3L/3U, LPDDR2/3
• Per-bit deskew for data/address/command, write leveling, data eye training, and PVT compensation
• Integration: GDSII hard macro + RTL PUB, programmable drive/ODT, and rapid controller/PUB integration
• I/O flexibility: 8–72 bits, 1–4 ranks, UDIMM/RDIMM/PoP, shared AC mode, and distributed PHY support