Smarter Signoff with Hierarchical STA

With design sizes expected to increase by 5X through 2020, flat chip-level STA becomes more challenging due to runtimes and memory requirements. Throwing more cores at the analysis can be a short term fix but may not keep up with chip complexity growth. This video provides an overview of the next generation of hierarchical STA, delivering a long term solution to this challenge. PrimeTime’s HyperScale methodology provides significant performance and memory advantages while utilizing existing compute resources from your server farm. This proven technology has been used in over 30 tapeouts.

Learn more about the PrimeTime® static timing analysis tool.

Watch all the videos in the Smarter Signoff video series.