DesignWare Multi-Protocol 16G PHY

The multi-lane DesignWare® Multi-Protocol 16G PHY IP is part of Synopsys’ high-performance multi-rate transceiver portfolio, meeting the growing needs for high bandwidth and low latency in enterprise applications. Using leading-edge design, analysis, simulation, and measurement techniques, the multi-protocol 16G PHY delivers exceptional signal integrity and jitter performance that exceeds the standards’ electrical specifications. The PHY is small in area and provides a low active and standby power solution that supports multiple electrical standards including PCI Express, SATA, Ethernet, OBSI/CPRI, JESD204, Serial Rapid I/O and other industry-standard interconnect protocols. The DesignWare Multi-Protocol 16G PHY IP is optimized to meet the needs of applications with high-speed port side, chip-to-chip, and backplane interfaces.

The configurable transmitter and receiver equalizers enable customers to control and optimize signal integrity and at-speed performance. Continuous Calibration and Adaptation (CCA) provides a robust performance across voltage and temperature variations during normal mode of operation. The PHY supports low standby power with advanced L1 substates and low active power with I/O supply under drive, decision feedback equalization (DFE) bypass and V-Boost off. The embedded bit error rate (BER) tester and internal eye monitor provide on-chip testability and visibility into channel performance. The PHY integrates seamlessly with the DesignWare Physical Sublayers and digital controllers/media access controllers (MACs) to reduce design time and to help designers achieve first-pass silicon success. These features reduce both product development cycles and accelerate time-to-market.

DesignWare Multi-Protocol 16G PHY IP Datasheet

 

Highlights
Products
Downloads and Documentation
  • Supports1.25 to 16 Gbps data rates
  • Supports
    • PCI Express 4.0/3.1/2 .1/1.1, with lane margining
    • IEEE 802.3 1G to 40G backplane (KX, KX4/XAUI, KR & KR4), port side (XFI, SFF-8431/SFI and CR4)
    • SGMII and QSGMII (1.25 to 5G)
    • SATA 6G/3G/1.5G
    • CEI-6G and CEI-11G
    • Serial Rapid IO (SRIO)
    • CPRI, OBSAI, JESD204B
    • Other industry-standards
  • Supports x1 to x16 macro configurations
  • Superior signal integrity across lossy backplanes enabled by a high-performance analog front-end that includes adaptive continuous time linear equalizer (CTLE), decision feedback equalization (DFE) and feed forward equalization (FFE)
  • PCI Express L1 substate power management
  • PCI Express Aggregation and bifurcation
  • Spread Spectrum Clock (SSC)
  • PCIe Separate Refclk Independent SSC (SRIS)
  • Reference clock sharing for aggregated macro configurations
  • Embedded bit error rate (BER) tester and internal eye monitor
  • IEEE 802.3az Electrical Energy Efficient (EEE)
  • Supports IEEE 1149.6 AC Boundary Scan
  • Supports -40°C to 125°C Tj
16G PHY, TSMC 16FFC x1, North/South (vertical) poly orientationSTARs Subscribe
16G PHY, TSMC 16FFC x4, North/South (vertical) poly orientationSTARs Subscribe
16G PHY, TSMC 28HPCP x1, North/South (vertical) poly orientationSTARs Subscribe

Description: 16G PHY, TSMC 16FFC x1, North/South (vertical) poly orientation
Name: dwc_16g_phy_tsmc16ffc_x1ns
Version: 1.01b
STARs: Open and/or Closed STARs
myDesignWare: Subscribe for Notifications
Product Type: DesignWare Cores
Documentation:
Download: E16-PHY_TSMC_16FFC_x1
Product Code: C256-0
  
Description: 16G PHY, TSMC 16FFC x4, North/South (vertical) poly orientation
Name: dwc_16g_phy_tsmc16ffc_x4ns
Version: 1.02c
STARs: Open and/or Closed STARs
myDesignWare: Subscribe for Notifications
Product Type: DesignWare Cores
Documentation:
Download: E16-PHY_TSMC_16FFC_x4
Product Code: C253-0
  
Description: 16G PHY, TSMC 28HPCP x1, North/South (vertical) poly orientation
Name: dwc_16g_phy_tsmc28hpcp_x1ns
Version: 3.00a
STARs: Open and/or Closed STARs
myDesignWare: Subscribe for Notifications
Product Type: DesignWare Cores
Documentation:
Download: 16G-PHY_TSMC_28HPCP_x1
Product Code: C306-0