DW_ram_rw_a_lat

IP Directory Component Detail
Description: Asynchronous Single-Port RAM (Latch-Based)
Name: DW_ram_rw_a_lat
Version: DWBB_202409.1
ECCN: EAR99/NLR
STARs: Open and/or Closed STARs
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Product Type: DesignWare Building Blocks
Overview: DesignWare Building Block Components
Documentation:
Examples: Direct Instantiation in Verilog
Direct Instantiation in VHDL