EDA
System
IP
SolvNetPlus
Training & Education
Scheduled Maintenance: DesignWare IP pages (synopsys.com/dw/) will be
unavailable on Friday, August 28, 2026 from 6:00 PM – Midnight PST
for planned system maintenance. Other synopsys.com pages will not be affected.
We apologize for any inconvenience.
DW_ram_2r_w_s_lat
coveo-noindex
IP Directory Component Detail
| Description: | Synchronous Write-Port, Asynchronous Dual Read-Port RAM (Latch-Based) |
| Name: | DW_ram_2r_w_s_lat |
| Version: | DWBB_202603.2 |
| ECCN: | EAR99/NLR |
| STARs: | Open and/or Closed STARs |
| myDesignWare: | Subscribe for Notifications |
| Product Type: | DesignWare Building Blocks |
| Overview: | DesignWare Building Block Components |
| Documentation: | |
| Examples: | Direct Instantiation in Verilog Direct Instantiation in VHDL |
Search Tools