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DW_ram_2r_w_s_dff
IP Directory Component Detail
| Description: | Synchronous Write-Port, Asynchronous Dual Read-Port RAM (Flip-Flop Based) |
| Name: | DW_ram_2r_w_s_dff |
| Version: | DWBB_201709.4 |
| STARs: | Open and/or Closed STARs |
| myDesignWare: | Subscribe for Notifications |
| Product Type: | DesignWare Building Blocks |
| Overview: | DesignWare Building Block Components |
| Documentation: |
Hide Documents... Application Note  DesignWare Building Block IP Application NotesDatasheet DWBB DW_ram_2r_w_s_dff DatasheetDoc Overview DesignWare Building Block IP Documentation OverviewRelease Notes DesignWare Building Block IP DC Release NotesUser Manual DesignWare Building Block IP User Guide |
| Examples: | Direct Instantiation in Verilog Direct Instantiation in VHDL |