While the adoption of 32 GT/s PCIe 5.0 technology is on an accelerated pace, SoC designers must understand and handle a few design challenges as they make the shift. 32 GT/s designs have challenging NRZ channels that are extremely lossy and bumpy with many discontinuities, with insertion loss reaching 36dB and beyond. The PCIe PHY design must encompass unique architectures with a proven analog front-end, continuous time linear equalizer, and advanced multi-tap decision feedback equalizer that seamlessly work together to mitigate design issues. Integrating the PHY and controller requires more careful planning to ensure compatibility at the PIPE interface and to facilitate timing closure at 1GHz.
Several PCIe 5.0 controller configuration options must be carefully selected and managed to achieve maximum performance. Architectural tradeoffs should be explored to balance maximum payload size, read request size, number of tags, and other important controller configuration settings.
Careful signal and power integrity analysis must be carried out for chips and packages, and the whole channel must be simulated to ensure performance targets are met at 32 GT/s.
These new challenges can be mitigated or eliminated by partnering with Synopsys, a proven and trusted IP partner with a track record of many years of success in developing high-quality PCIe IP. The Synopsys DesignWare® IP complete solution for PCIe 5.0 includes controllers, PHYs and verification IP. The silicon-proven IP supports the PIPE 4.4.1 and 5.1.1 specifications, using architectures allowing more than 36dB channel loss and enabling straightforward 1GHz timing closure. The controller is highly configurable with support for multiple data path widths, including a tested, silicon-proven 512-bit architecture and provides the industry’s most extensive RAS-DES features to enable seamless bring up and debug. The silicon-proven solution, already adopted by many customers, provides the full IBIS-AMI models needed to accurately simulate PCIe systems.
1From Real-time oscilloscope analysis for 28/32-Gbps SerDes measurements, a Whitepaper by Brig Asay, Agilent Technologies, December 17, 2012