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Marvell: Accelerating Interposer Design with Early Signal Integrity Analysis

Date: Apr 28, 2026 | 9:00 AM PST

In this webinar, Marvell will present how its team accelerates passive interposer routing for advanced 2.5D/3.5D multi die designs by bringing early, physics based signal integrity feedback into each routing iteration. Rather than relying on repeated, compute intensive 3D FEM cycles during development, Marvell uses a Method of Moments (MoM) early SI check available within Synopsys 3DIC Compiler to evaluate routing with real parasitics and simulation data, fast enough to support rapid iteration and safer exploration of auto routing strategies.  Marvell will also share practical correlation takeaways, where MoM tracks FEM strongly and where additional margin and correlation work may be needed ahead of final signoff.

What you’ll learn

  • Why traditional interposer SI signoff can become a major schedule bottleneck
  • How early SI analysis with MoM differs from FEM and where it fits best
  • How to use physics-based SI feedback during interposer routing iterations
  • When and how to correlate early SI results with FEM for confidence and margin
  • How early SI enables faster convergence and broader design space exploration

Register Now

Featured Speakers

Nitin Navale
Senior Principal CAD Engineer, Marvell
 
Nitin Navale currently serves as 3DIC Methodology Lead at Marvell Semiconductor. He previously worked at AMD & Xilinx for nearly 20 years, where he contributed to CAD & Methodology across a wide range of disciplines spanning 3DIC, Signoff, RTL/Netlisting, and Physical Verification. Nitin earned his BS and MS in Electrical Engineering from the University of Illinois, Urbana-Champaign. Outside work, he is consumed by his devotion to gaming, strategy, and music.

Adish Mehta
Senior Staff Engineer, Marvell
 
Adish Mehta is a seasoned semiconductor professional specializing in EM/IR signoff, power integrity, and signal electromigration analysis for advanced SoC and multi-die designs. He has led the development of scalable, hierarchical, and in-context signoff methodologies that improve reliability and design efficiency across bleeding-edge technology nodes. Adish frequently collaborates with global design teams, foundries, and EDA vendors to drive innovation in power and reliability analysis, helping deliver robust, production-ready silicon across a variety of platforms.