This Synopsys webinar shares real-life examples of how to execute clock gating verification with a well-defined methodology using the Synopsys VC Formal Sequential Equivalence Checking app. By the end of this Synopsys webinar, you will be able to uncover corner case clock gating bugs that are difficult to verify with simulation.
This Synopsys webinar is part one of a two-part series. This series will teach clock gating formal verification for any level user – from basic concepts to advanced topics. Part one is prepared for engineers who are new to this area of expertise. Part two is for experienced RTL designers and verification engineers who want to design high-quality clock gating circuits and verify with confidence.
Guest presenter, Xiushan Feng, will share his more than 10 years’ experience in this specific area to demonstrate how you can formally verify clock gating designs with a high confidence.