Today’s million gates integrated circuits (ICs) involve various intellectual properties (IPs) interfacing with each other through multiple asynchronous clock and reset domains. Ensuring all clocks propagate concurrently across each clock tree components used as clock switching elements or each sequential or combinatorial component, clock output of which becomes asynchronous with respect to the clock input while maintaining predictability of design functionality requires exhaustive CDC verification.
In addition to relying on a robust design specification, it becomes imperative to take advantage of a smart EDA tool that infers all critical design paths including all clocks, clock control signals, clock domain at IP’s boundary level and even the resets for CDC or RDC paths ultimately flagging any unpredictable design behavior. VC SpyGlass CDC and RDC completely meets these verification needs by back-tracing and reporting all signals that needs to be constrained for optimized coverage of the structural verification, eventually delivering high quality of results (QoR) for CDC and RDC analysis.
Proceeding this way prevents the direct reuse of STA (Static Timing Analysis) constraints that may lead to an optimistic configuration, such as the propagation of synchronous clocks instead of asynchronous ones, or other mismatches between CDC analysis and STA, which would limit the number of the analyzed CDC paths.
In this web seminar, we will present the different steps required to manage the constraints generation and elaboration during CDC and RDC analysis. An efficient static low-power verification approach concerning low-power components defined through the UPF file directives will also be illustrated. Lastly, we will conclude by demonstrating ways to manage the different aspects of constraints using VC SpyGlass as an open tcl tool allowing the elaboration of additional and custom features increasing the QoR compared to the native platform.