EDA
System
IP
SolvNetPlus
Training & Education
Achieve High Product Quality with Algorithmic Testing of Interconnect and DRAM
Synopsys SLM ext-RAM is a comprehensive, user programmable high-quality test and diagnostics solution for logic-to-memory interconnect and DRAM memories. This fully synthesizable algorithmic engine can support various protocols such as DDR/LPDDR/HBM and cHBM (custom HBM) and is process technology, foundry and DRAM vendor agnostic. With the provided scripts and reference design, SoC designers can leverage ext-RAM across the silicon lifecycle by accelerating time to closure during design, maximizing yield during production and increasing reliability in-field
Common use case scenarios for customers leveraging multi die (2.5D/3D-IC) designs include those who ship full systems or multi-chip modules (MCM). The Synopsys SLM ext-RAM is commonly deployed in conjunction with the SLM STAR Hierarchical System (SHS) which in turn can be used to automatically initialize the memory PHY via JTAG using pre-validated ATE patterns (for Synopsys PHYs) before initiating DRAM testing
Key Benefits
Features
- Enhanced Reliability: Supports Test, Diagnostics along with BIRA (Built In Redundancy Analysis)* and Post Package Repair (PPR)* to improve in-field reliability
- High Test Coverage: Addresses all common set of DRAM fault models including stuck-at, coupling, transition, read/write destructive, write mask, address decoder and row hammering
- Flexible Use Cases: User can load additional test sequences to programmable Test Algorithm Register (TAR) post-silicon
- User Programmability: Offers programmability for addressing modes and types, address ranges, chip selects, looping mechanism, background patterns, data patterns, timing, DQ trimming and PHY latency
- Advanced Diagnostics: Stop-on-Nth Error (SONE) Diagnosis with multi level diagnostic information