Synopsys XBC/XHC OTP NVM IP SLP Architecture Datasheet

Access the Synopsys XBC/XHC OTP NVM IP Datasheet and discover how SLP‑based anti‑fuse technology delivers secure, fast, low‑power one‑time‑programmable memory—manufactured with no additional masks or process steps—for SoC applications such as trim and calibration, RFID, secure boot, encryption‑key storage, and firmware protection.

What You Will Learn:

• How the SLP anti‑fuse architecture provides intrinsic security and serves as a low‑power alternative to mask ROM, eFuses, and Flash.
• How the XBC/XHC OTP IP integrates easily into SoCs with a hard‑macro memory array and optional integrated power supply for single‑ or dual‑supply operation.
• How flexible memory options (1Kbit–256Kbit) and multiple read modes enable optimized area, speed, and power across applications on standard CMOS at 180nm and 152nm.