Jitter Budgeting for Clock Distribution Networks in High-Speed PHYs and SerDes White Paper

The “Jitter Budgeting for Clock Distribution Networks in High‑Speed PHYs and SerDes” white paper presents a practical and accurate method for estimating power‑supply‑induced jitter (PSIJ) in MOS clock buffer chains. As modern PHYs and SerDes operate at increasingly higher data rates, power‑distribution‑network (PDN) noise has become a dominant source of deterministic jitter. This paper introduces a closed‑form analytical approach that enables designers to budget timing uncertainty early—before detailed circuit implementation—using minimal simulation inputs.

What You Will Learn:

• Why power‑supply‑induced jitter dominates clock uncertainty in advanced PHYs
• How PSIJ manifests as period jitter, N‑cycle jitter, and maximum TIE
• How analytical jitter estimation replaces complex frequency‑domain models