Synopsys DDR3/2 PHY IP Datasheet

Download the Synopsys DDR3/2 PHY IP datasheet and see how a silicon-proven, GDSII-based hard PHY delivers up to 2133Mbps, JEDEC DDR3/3L/2 compatibility, and robust per-bit deskew for rapid timing closure and risk-free integration.

What You Will Learn:

How to implement a GDSII-delivered, low-power PHY supporting DDR3 (2133Mbps) and DDR2 (1066Mbps)
Integration: DFI 2.1-compliant controller interface, rapid hookup with Synopsys protocol/memory controllers
Signal integrity: programmable drive strength/ODT, dynamic PVT compensation, per-bit deskew, and flexible I/O ring

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