An ASIP is only worth developing if it can bring useful differentiating advantage within that design’s market window. Designers therefore need to be able to rapidly explore the impact of architectural choices upon their ASIP, by doing three things:
1. Define benchmarks representative of the end application, to enable a quantitative comparison of the architectures being considered. A benchmark must have:
- A functional specification, describing the application kernels that need to be implemented. Benchmarks are usually represented in C for ease of implementation and architectural independence.
- An environment describing the stimuli that exercise the benchmark.
- Performance metrics such as power, performance, and target frequency.
2. Describe a candidate architecture
Designers need a quick and easy way to define a candidate architecture, ideally using a modelling approach that avoids specifying deep implementation details early in the design process.
Designers also need software tools to map benchmark code onto the candidate architectures, and, since it is impractical to develop a new toolchain for each candidate architecture manually, this needs to be automated.
3. Explore the design space
Design exploration involves evaluating each candidate architecture against the defined benchmarks. There are two main concepts to be applied to this.
Compiler-in-the-loop: Designers need to use a C/C++ compiler to run benchmarks onto each candidate architecture, rather than trying to use time-consuming and error-prone assembly language. It’s also mandatory to have a cycle-accurate instruction set simulator (ISS) and a profiler to analyze results. The C/C++ compiler, ISS and profiler can be combined with a debugger, assembler, and linker to form a full software development toolkit (SDK).
The SDK should be available early in the design process and quickly retargetable to the various architectural alternatives, to enable efficient design-space exploration.
Synthesis-in-the-loop: It can be useful to quickly analyze the hardware cost and characteristics of a candidate architecture in terms of its operating frequency, area, and power efficiency. To do this, there should be a way to automatically generate synthesizable RTL, and then use synthesis tools to analyze the hardware characteristics of each candidate architecture.