Pre-Design Verification and Optimization for On-chip Interconnects

Data movement plays a big role in overall SoC performance. It is essential to qualify the on-chip interconnect architecture as early as possible - to verify algorithms applied on the on-chip interconnect, determine the best performance tuning settings in the design, and assist in power and performance projections - all before RTL is available.

This presentation discusses the collaboration between Microsoft and Synopsys on the on-chip interconnect model development and exploration using Platform Architect, the many learnings that were made along the way, and the achievements made by the team.