EDA
System
IP
SolvNetPlus
Training & Education
SNUG India - Bangalore 2019 Proceedings
Complete Proceedings
2019 SNUG India - Bangalore Award Winners for Best Paper
AMS
Need for Iterative MOS Reliability Analysis for High Voltage Level Shifter of IO Buffers
IC Implementation
The "Art" of Gauging Crosstalk Delay Accuracy and the "Science" of Taking it to Closure
IC Implementation
Parallel Per-Critical-Clock (PPCC) Logic Synthesis and Netlist Fusion for Best PPA and Convergence
Systems & IP
Accelerating Design Cycles with Software Workload Models and Cycle Accurate Hardware Models A Home Gateway SoC Case Study