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Training & Education
From Copper to COUPE: Scaling AI Interconnects with Co-Packaged Optics
Date: Sep 17, 2026 | 9:00 AM PST
Featured Speakers:
- Igor Elkanovich, CTO, GUC
- Sheng-Fan Yang, Director, GUC
- Madhumita Sanyal, Sr. Director Product Management, Synopsys
Co-packaged optics (CPO) breaks through the data movement constraint by moving optical engines next to the XPU, reducing electrical reach from centimeters to millimeters and delivering the bandwidth density and energy efficiency that copper can no longer provide. In this webinar, Synopsys and GUC share their experience building CPO-enabled XPUs on TSMC COUPE, from high-speed interface IP through multiphysics signoff and manufacturing.
Join experts from Synopsys and GUC as we walk through real design and integration challenges, spanning EIC-over-PIC 3D stacking, high-speed 224G and UCIe interfaces, thermal analysis, and the path to volume manufacturing and test.
What You'll Learn:
- Why AI scale-up and scale-out fabrics are driving CPO, and where ESUN and UALink fit
- How 224G and UCIe IP enable high-bandwidth, low-power optical engines in COUPE
- How GUC transforms COUPE into production-ready optical XPUs through advanced-packaging and 2.5D/3D integration expertise
- Proven results solving COUPE implementation challenges: EIC/PIC co-design, hybrid bonding, and interposer/RDL integration
- How Synopsys and GUC co-optimize XPU thermal behavior with optical engines using Synopsys multiphysics analysis technologies
- How GUC's turnkey ASIC, manufacturing, and test flow delivers volume-ready CPO for AI systems
Register Now
Featured Speakers
Currently, he serves in GUC as a director, leading SI/PI/TI/MI division, for chip/package/system high speed integrated designs of AI ASIC products. His research interest includes high speed heterogeneous integration of 2D/2.5D/3D-IC, e.g., 112G/224G-SerDes, UCIe-A/S, HBM3/4, and multi-physics co-analysis.
