Verification Videos

A Gentle Introduction to Formal Verification

Getting started with Formal Verification can be intimidating for engineers with a design or functional simulation background. This can happen due to a few common reasons depending on how much exposure you've had to Formal, such as:

• Hard time drawing parallels between Formal and UVM simulation
• Unfamiliarity with writing assertions
• A fear of signing-off on verification with Formal

The intention of this presentation is to address any concerns and convince the audience that if you're a Designer or a DV engineer, Formal Verification is your new best friend.

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