EDA
System
IP
SolvNetPlus
Training & Education
Synopsys SLM UCIe Monitor, Test & Repair (MTR) IP is a fully synthesizable RTL solution that enables monitoring, test, and repair of UCIe die-to-die interconnects for advanced multi-die systems. Supporting both UCIe Standard (UCIe-S) and UCIe Advanced (UCIe-A) PHYs, the IP delivers high-quality production test, accelerates silicon bring-up, and enables mission-mode health monitoring for improved reliability and availability.
The solution operates independently of foundry and process technology, leveraging Signal Integrity Monitors (SIMs) embedded in Synopsys UCIe PHYs to provide real-time eye margin information and proactive degradation detection. It integrates seamlessly with standard JTAG/IEEE 1149.1 infrastructure during manufacturing test and APB interfaces for in-system lifecycle management.
Key Benefits
- Superior Product Quality: Deliver high-quality die-to-die interconnect test coverage using algorithmic and user-defined test patterns that detect coupling, crosstalk, and other interconnect faults.
- Faster Silicon Bring-Up: Accelerate production test, post-silicon debug, and system validation by replacing complex external probing approaches with embedded monitoring and test infrastructure.
- Mission-Mode Reliability: Continuously assess interconnect health during operation and proactively identify degrading links before catastrophic failures occur.
- Efficient Repair Management: Automate storage and retrieval of repair signatures using eFuse integration while supporting standard and cumulative repair methodologies.
- Broad Deployment Flexibility: Support both UCIe-S and UCIe-A PHY implementations across multiple UCIe generations while remaining independent of foundry and process technologies.
Key Features
- Embedded Signal Integrity Monitoring: Access near-side SIMs within the UCIe PHY to collect eye parameter and margin information during mission mode.
- Algorithmic and User-Defined BIST: Execute die-to-die and loopback testing using built-in algorithms or custom user-specified patterns.
- Production and In-System Access: Operate through standard JTAG/IEEE 1149.1 interfaces during manufacturing and APB interfaces during system deployment.
- Advanced Lane Repair Support: Read and write UCIe PHY reconfiguration registers and store/retrieve repair signatures via eFuse integration.
- Autonomous Monitoring: Collect and analyze eye-margin measurements with programmable thresholds and interrupt-based notification mechanisms.
- Compact Area Footprint: Optimized architecture minimizes gate count and silicon overhead while leveraging Synopsys PHY capabilities.
- Fully Synthesizable RTL: Compiler-generated implementation supports simplified integration across a broad range of process nodes and foundries.