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Juniper Highlights IC Validator’s Performance Benefit: Overnight Full Chip DRC and LVS
Customer Experience
At the IC Validator panel at SNUG Silicon Valley 2018, Juniper shares their experience with IC Validator. Full chip physical verification runtime is a big challenge to designers at the advanced process nodes. In this video, Juniper highlights how IC Validator demonstrated overnight runtimes for DRC and LVS checking of Juniper’s full chip designs.
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