ESP Bridging the Gap Video Series

Formal Verification for Custom Digital Design

Synopsys ESP is an equivalence checker for full custom designs. It enables fast and reliable comparison of a Verilog reference design against a transistor-level SPICE netlist. It is ideally suited for a wide range of custom digital applications, including:

• Compiled and custom memories (i.e. CAM, SRAM, ROM, etc.)
• Datapath blocks
• Programmable Logic (FPGA)
• Standard cell and I/O libraries