Arm-based SoC designs are driving the next wave of product and market innovation. These SoCs are architected to deliver superior connectivity, improved security, increased processing power, longer battery life, and advanced AI for the next generation of consumer, high-performance computing, and data-center products. Synopsys and Arm have a long history of R&D collaboration, leading to solutions that enable mutual customers to accelerate their software development, co-verification of hardware and software, and quality of Arm-based designs. These solutions utilize the Synopsys Fusion Design Platform and Verification Continuum Platform, HAPS FPGA-based prototyping systems, Virtualizer virtual prototyping and Platform Architect MCO architecture design toolsets, and DesignWare IP.
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Arm & Synopsys
Pioneering Innovative Technologies With a Shift-left Approach to Address Mutual Customers' Complex SoC Challenges
Latest News
Synopsys Enables First-Pass Silicon Success for Early Adopters of Next-Gen. Armv9 Architecture-based SoCs
Design, Verification, and IP Solutions Combine to Deliver a Total-Compute-centric Solution That Enables Maximum Performance-Per-Watt for High-End Consumer Devices
Synopsys and Arm Deliver Comprehensive Solutions to Increase Performance and Accelerate TTM for HPC, Data Center and AI SoCs
Arm Extends Strategic Agreement with Synopsys for EDA Platforms, IP and Reference Flows for Arm's Next-Gen. Neoverse V1 and N2 Platforms
Arm Leverages Synopsys Fusion Compiler to Enable Best PPA for Latest Neoverse Platforms
Architecturally Targeted Optimizations Accelerate the Development of Arm Neoverse V1 and N2 Platforms; Deliver Best-In-Class Performance-Per-Watt
Latest Arm-Focused Resources
Designer's Digest: Achieving the Best Arm PPA using Jointly Developed Flows & Methodologies
Learn MoreAddressing Power Integrity with an Easy Signoff Ready Methodology for Next-Gen. Arm® Cores
Watch NowAttain the Best PPA on Advanced Arm® Cores with Fusion Compiler’s New Placement Technology
Watch NowArm
- Paul Williamson
SVP and GM, Client Line of Business
"Our broad collaboration with Synopsys has enabled us to push the industry's achievable performance-per-Watt for highly pervasive computing in the client compute market." Read More
Arm
- Ciaran Dunne
Vice President and General Manager, Partner Enablement Group
"Our strategic collaboration with Synopsys over the last three decades enables our mutual customers to implement high-performance and energy-efficient Arm-based SoCs. Working closely with Synopsys during pre-beta IP development stages allows us to provide complete solutions that address a range of markets from mobile to the infrastructure." Read More
Arm
- Chris Bergey
SVP and GM, Infrastructure Line of Business
"The pace of innovation happening in this next era of computing underscores the importance of faster time-to-market for SoCs. The deployment of Synopsys functional verification solutions on AWS Graviton2 processors demonstrate the growth of Arm in the cloud. We look forward to what our mutual customers will bring to market using the growing set of EDA tools now available on Arm." Read More
Arm
- Tran Nguyen
Senior Director of Design Services
"As more software-intensive Arm-based HPC, 5G, GPU, AI and automotive applications are developed, there is an increasing demand for faster emulation and accelerated verification, and we continue to work closely with Synopsys to address that need for our mutual customers." Read More
Samsung
- Jaehong Park
Executive Vice President of Foundry Design Platform Development
"Synopsys' Fusion Design Platform and QuickStart Implementation Kits provide a design-ready solution for next-generation Arm-based processors. This is a great example of how Samsung 5LPE technology can be utilized to give designers a competitive advantage in their high-performance CPU designs." Read More
Ten Arm-Focused Sessions at SNUG World
Register now to watch SNUG World 2021. Hear from Arm and Synopsys technical experts and your peers about the latest methodologies, technologies, and strategies enabling revolutionary Arm-based SoCs.
Arm - Synopsys Presentations
Achieving the Best PPA on Advanced Arm Cores with Fusion Design Platform (Digital Design Track)
Arm and Synopsys experts will highlight the best practices, new methodologies, and co-developed enabling technologies that deliver the industry's leading power, performance, and area (PPA) for the latest Arm cores, targeted for smartphones, laptops, hyper-scale cloud computing, 5G infrastructure, and beyond.
Pierre-Alexandre Bou-Ach, Arm; Shankar Vellanthurai & Gary Rudolph, Synopsys
Cost-Effective Characterization on Arm-based AWS Graviton2 Processors (Signoff II Track)
Cloud computing offers amazing scalability with the right mix of software and configuration, thereby helping us meet the compute demands emanating from our time-to-market requirements. This is where Arm based AWS Graviton2 processors comes into picture, they are not only fast but also cost effective hence execution on Arm-powered cores, instead of the conventional x86-powered cores.
Ajay Chopra, Arm
Mitigating Soft Errors Impact on System Reliability (Automotive Track)
Reliability, availability and serviceability is a major concern for cloud applications. A deep analysis can identify the portions of the design that can cause the system to behave unpredictably in the presence of soft errors. Statistical analysis based on probability of error propagation in the design can be performed in large complex systems; we will present our findings based on the static analysis approach used in TestMAX FuSa.
Ghani Kanawati, Arm
QuickCap Parasitic Extraction for Arm Physical Design (Signoff II Track)
This presentation will give an overview of our experience with Quickcap for Parasitic Extraction. We will review the extraction performance compared to our standard flow for production, extraction accuracy, usability and readiness with respect to Arm Physical Design IP production.
Tom Mahatdejkul, Arm
Buried Signal Line Exploration for Sub-5nm SRAM Design (Signoff II Track)
Buried power rail (BPR), i.e., metal wires below the active transistors, has been proposed for routing power and ground lines to improve the performance and density of standard cells and mitigate the increasing RC parasitics at sub-5nm CMOS technology nodes. We will present the Buried Bit-Line (BBL) SRAM technique which utilizes buried metal interconnects for signal routing instead of power or ground routing to achieve better SRAM performance and lower power consumption while requiring minimal process flow changes to the buried power rail technology. We will show how design technology co-optimization (DTCO) is performed using Synopsys Quickcap for high-accuracy parasitic extraction of buried metal rail to identify optimal BBL parameters.
Rahul Mathur, Arm
Functional Equivalence Check of Industry’s First eMRAM Using Synopsys’ ESP (Signoff II Track)
Magneto-resistive Random Access Memory (MRAM) combines a magnetic device with standard silicon-based microelectronics to obtain the combined attributes of non-volatility, high-speed and unlimited read and write endurance. In this presentation, we would be focusing on how Synopsys’s ESPCV enabled us in the validation of industry’s first eMRAM macro. We will mostly be focusing on the challenges that we faced and how ESPCV helped in overcoming them during the functional validation of eMRAM without impacting our delivery timelines.
Jeevan Buddhi, Arm
Frequency vs. Time Done Right: Designing a High-Performance Arm POP IP Solution with Minimal Turn-around Time Using Synopsys Fusion Compiler™ (Digital Design Track)
As we move towards faster and more powerful devices and ever-smaller technology nodes; we have slowly pushed the number of transistors on a single CPU to soaring levels. This makes the most of the reduction in transistor size and leakage on the latest foundry nodes while pushing the performance of the core to never-seen-before maxima. However, the burgeoning instance count coupled with increasing design and routing complexity exacts a heavy toll on our EDA tools as well as traditional optimization techniques, resulting in extremely large TAT and machine resource usage. In this presentation, we address the solution to this dilemma – the novel CPU POP solution enabled by using Synopsys Fusion Compiler™.
Viswanath Akash, Arm
Customer Presentations
Samsung: Estimating DVD-Induced Timing Impact Using PrimeTime® and RedHawk-SC
April 20: 12:00 PM - 12:25 PM
(Signoff II Track)
In this work, PrimeTime's new DVD analysis has been proved. The new method of PrimeTime is able to directly read Redhawk-SC's DVD report and estimate its impact on timing. It is shown that the new method is well correlated with quad-core ARM CA53 chip implemented in Samsung's LN10LPP process.
Speaker: Jongyoon Jung
Nokia Networks: Virtualized CPU Usage in SoC Verification
April 21: 10:00 AM - 10:25 AM
(Virtual Prototyping Track)
A virtual fast model of ARM Cortex-A55 microarchitecture is used implementing the ARMv8.2-A 64-bit instruction set. The VCPU was compared to AXI VIP connection to find out differences between traditional verification and co-verification flow. Measurements indicate that co-simulation with VCPU has very good performance compared to traditional verification.
Speaker: Mika Mäenpää
ST Microelectronics: How to Achieve the Best PPA on an Ultra-Low Power STM32 Microcontroller; SAIF Driven Synthesis Flow
April 21: 11:25 AM - 11:50 AM
(Low Power Design)
This presentation will highlight a methodology to achieve the best performance, power & runtime results with an RTL SAIF-driven synthesis flow on an ultra-low power Arm microcontroller-based design with multiple switchable power domains embedding retention registers.
Speaker: Nathalie Meloux
Arm Core Solutions and Services
Optimized Implementation
Solutions for optimizing Arm processor and SoC power, performance, area
Learn MoreHW/SW Design & Integration
Virtual prototype, architecture design solutions for early SW development
Learn MoreHardware Design & Verification
IP, verification solutions for Arm processor and AMBA interconnect SoCs
Learn MoreArm Core Hardening & Optimization
Our Core Hardening & Optimization Consultants are available to help.
Learn MoreQuickStart Implementation Kits
Arm® core QIKs provide scripts, a floorplan, design constraints & documentation for optimized implementations.
Learn More