In this Synopsys webinar, we will discuss how to reduce the time-to-first-test from weeks to hours by automating the process of testbench generation with Synopsys VC AutoTestbench. We will also include a demo of this flow using a real-world design and Synopsys VIP for Arm® AMBA® protocol. Specifically, you will learn:
- How to quickly and easily generate a complete SystemVerilog/UVM verification environment
- How to efficiently reuse SoC-level testbenches for IP & interconnect verification
- How to bring-up the auto-generated testbench and run tests from the Synopsys VIP test suites for AMBA protocol
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